Monday, 29 August 2016

Nielit A Level January, 2015 A4-R4: COMPUTER SYSTEM ARCHITECTURE

Nielit A Level January, 2015
A4-R4: COMPUTER SYSTEM ARCHITECTURE

NOTE:
IMPORTANT INSTRUCTIONS:
1. There are TWO PARTS in this Module/Paper. PART ONE contains FOUR questions and PART
TWO contains FIVE questions.
2. PART ONE is to be answered in the OMR ANSWER SHEET only, supplied with the question
paper, as per the instructions contained therein. PART ONE is NOT to be answered in the
answer book.
3. Maximum time allotted for PART ONE is ONE HOUR. Answer book for PART TWO will be
supplied at the table when the answer sheet for PART ONE is returned. However, candidates,
who complete PART ONE earlier than one hour, can collect the answer book for PART TWO

immediately after handing over the answer sheet for PART ONE.
TOTAL TIME: 3 HOURS TOTAL MARKS: 100
(PART ONE – 40; PART TWO – 60)

PART ONE
(Answer all the questions)

1. Each question below gives a multiple choice of answers. Choose the most appropriate one and enter in the “OMR” answer sheet supplied with the question paper, following instructions therein. (1x10)

1.1 ________ is a circuit which has two stable states and can be used to store information.
A) Flip-flop
B) Logic circuit
C) Boolean circuit
D) Relational circuit

1.2 ________ selects one output signal from many input signals, hence it is also known as data
selector.
A) Encoder
B) Decoder
C) Multiplexer
D) Comparator


1.3 For a binary adder which adds two four bit binary numbers, how many half adders and full
adders are required?
A) 3 half adders and 1 full adders
B) 2 half adders and 2 full adders
C) 1 half adder and 3 full adders
D) 4 half adders

1.4 Components of a typical IEEE floating point number are:
A) Sign bit and binary number
B) Sign, exponent and the complete binary number
C) Sign, exponent and mantissa
D) Sign bit and exponent

1.5 -51 in 2’s complement form in total 7 digits:
A) 1110011
B) 1001101
C) 0110011
D) 1001100

1.6 Dyadic operations are those operations that require ________ operands to produce a result.
A) One
B) Two
C) Three
D) Four

1.7 Performing a three position, right logical shift on the number 10110001 results in:
A) 00110110
B) 10001001
C) 00010110
D) 10110111

1.8 ________ is an input device that detects two-dimensional motion relative to a surface. This
motion is typically translated into the motion of a pointer on a display, which allows for fine
control of a graphical user interface.
A) Mouse
B) Keyboard
C) Screen
D) CRT

1.9 It is a method of transferring data from the computer's RAM to another part of the computer
without processing it using the CPU.
A) Pipelining
B) DMA
C) Copying
D) Moving

1.10 What is used by an assembly language to represent each low-level machine operation or
opcode?
A) Variable
B) Mnemonic
C) Labels
D) All of the above

2. Each statement below is either TRUE or FALSE. Choose the most appropriate one and ENTER in the “OMR” answer sheet supplied with the question paper, following instructions therein. (1x10)

2.1 Output of an AND gate is low if any one of the input signals to the gate is low.
2.2 A NAND gate is equivalent to an inverted – inputs OR gate.
2.3 Zero address instruction has minimum one address field.
2.4 Unicode is an American standard code for information interchange, which is a characterencoding
scheme originally based on the English alphabet that encodes 128 specified
characters.
2.5 If a memory has n cells, the addresses can be 0 to n+1.
2.6 Virtual memory combines the computer’s RAM with temporary space on the computer’s hard
disk. When RAM runs low, virtual memory moves data from RAM to a space called a paging file
to make RAM free in order to complete the task.
2.7 A pipeline is a set of data processing elements connected in series, where the output of one
element is the input of the next one.
2.8 Computers can read from CD-ROMs and on need writes frequently on the CD-ROMs.
2.9 Every time you open a program, it gets loaded from the RAM to the hard drive of the computer.
2.10 For a tri-state buffer, if input is low, output is also low.

3. Match words and phrases in column X with the closest related meaning/word(s)/phrase(s) in column Y. Enter your selection in the “OMR” answer sheet supplied with the question paper, following instructions therein. (1x10)

                              X                                                                        Y

3.1 All possible alternatives of                                   A. Assembly programming language
input variables and corresponding
output
3.2 One input signal to the gate and one                   B. 1 GB (gigabyte)
 output signal from the gate
3.3 A limitation of sign magnitude method              C. SIMD
3.4 Fills given bit (with 0 or 1) in such a                  D. Even parity
way that total number of 1’s in the original
 binary number including the check bit
becomes odd
3.5 Array processor                                                   E. MIMD
3.6 1024 Megabytes                                                  F. NOT gate
3.7 Locality principle                                                G. 1 MB (megabyte)
3.8 Flash memory (electrically erasable                   H. Synchronous Transmission of data
programmable read-only memory)
3.9 The time interval between two characters is        I. Pen drive
fixed and constant while data transmission.
3.10 Low level programming language                    J. Truth table
                                                                                  K. Cache memory
                                                                                  L. Odd parity
                                                                                M. Positive and negative zeroes

4. Each statement below has a blank space to fit one of the word(s) or phrase(s) in the list below. Enter your choice in the “OMR” answer sheet supplied with the question paper,following instructions therein. (1x10)

A. An arithmetic and logic                 B. Cache                                              C. Gate
unit (ALU)
D. Immediate                                      E. Memory counter                             F. Keyboard
G. Modulation                                   H. Nibble                                              I. Printer
J. Program Counter (PC)                   K. RISC                                                 L. Touch Screen
M. Trap

4.1 ________ is a logic circuit with one or more inputs but only one output.
4.2 A group of four bits is called a ________.
4.3 ________ is a CPU design strategy which emphasizes use of small and simple instructions that
can be executed within one clock cycle instead of complex instructions.
4.4 While executing instructions, the address of next instruction to be fetched from the memory
address is specified in the ________.
4.5 ________ memory is a smaller, faster and costly memory which stores copies of the data from
the most frequently used main memory locations.
4.6 ________ is a digital circuit unit that performs arithmetic and logical operations. It is also
considered as the fundamental building block of the central processing unit of a typical
computer.
4.7 When an instruction itself contains the operand (data) rather than the address of the operand,
the technique is known as ________ addressing.
4.8 A ________ is a kind of automatic procedure call initiated by some condition caused mainly by
the program. It is also known as exception or fault.
4.9 By varying the amplitude, frequency or phase, sequence of 0 and 1 can be transmitted. This
process is known as ________.
4.10 A ________ is an electronic visual display that the user can control through simple or
multi-touch gestures by touching the screen with a special stylus/pen and-or one or more
fingers.

PART – TWO
(Attempt any FOUR questions)

5.
a) Explain the construction with logic diagram of a 4 – 1 line multiplexer.
b) Design a logic circuit that considers a six bit word and passes it, if a positive signal is given.
c) Draw logic circuit for the following Boolean equations:
i) Output= (X+Z) (Y’+Z) (X’+Y+Z)
ii) Output= (ZX+Y’Z +X’YZ )’
(5+5+5)
6.
a) Draw logic circuit for 2’s complement adder subtractor. Explain its working by taking a suitable
example.
b) Represent 40.15625 into 32 bit IEEE floating point format.
c) Draw circuit diagram for SR latch built with NAND gates. Also provide its truth table.
(5+5+5)
7.
a) List & explain steps in the fetch-decode-execute cycle of the instructions.
b) Explain in brief the direct and indirect addressing techniques.
c) Differentiate traps and interrupts.
(5+5+5)
8.
a) Explain the working of DMA transfer mechanism.
b) Explain general steps of the Booth’s algorithm. Use the algorithm to multiply 7 and 3.
(7+8)
9.
a) Explain working of a typical laser printer.
b) Write an assembly program to add two 16 bit numbers. Also extend the program to display the
result.
(7+8)

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