Thursday, 1 September 2016

NIELIT A Level July, 2010 A4-R4: COMPUTER SYSTEM ARCHITECTURE

NIELIT A Level July, 2010
A4-R4: COMPUTER SYSTEM ARCHITECTURE


PART ONE
(Answer all the questions)

1. Each question below gives a multiple choice of answers. Choose the most appropriate one and enter in the “tear-off” answer sheet attached to the question paper, following
instructions therein. (1x10)
1.1 Which of the following is NOT the key distinguishing feature of a microprocessor
A) Clock Speed
B) L1 Cache
C) Number of transistors
D) Capacity of the Hard Disk
1.2 The two's complement of binary number 11001 is
A) 00111
B) 00110
C) 11000
D) 11001

1.3 How many binary digits are added by a full adder
A) 12
B) 3
C) 4
D) 2
1.4 A NOR gate is ON only when all its inputs are
A) ON
B) Low
C) Oscillating
D) OFF
1.5 A disk pack contains 6 disks. Data can be read/written from both the surfaces of the disk.
There are 200 tracks on each disk surface, each track is divided into 50 sectors and each
sector contains 512 bytes. What is the total storage capacity of the disk pack (in bytes)?
A) 512X50X200X12
B) 512X50X200X10
C) 512X50X200X6
D) (512X50X200X6)/2
1.6 The number of input words in a truth table always equals ________, where n is the number of
input bits
A) 10n
B) 2n
C) 4n
D) 8n
1.7 Which of the following semiconductor memory is used for cache memory?
A) SRAM
B) DRAM
C) ROM
D) PROM
1.8 The result of adding numbers -7 and 5 in two's complement representation is
A) 1110
B) 1010
C) 1001
D) 1100
1.9 The meaning of the instruction ISZ X (increment and skip if zero) is
A) Increment the content of accumulator by one, if it is zero then skip to the location X.
B) Increment the locations X by one if it is zero then skip the next instruction
C) Increment the content of location X by one, if the result is zero, skips the next instruction.
D) None of these
1.10 In which addressing mode the operator is included in the instruction format
A) Indirect Addressing
B) Direct Addressing
C) Immediate Addressing
D) Indexed Addressing

2. Each statement below is either TRUE or FALSE. Choose the most appropriate one and ENTER in the “tear-off” sheet attached to the question paper, following instructions therein. (1x10)

2.1 In boolean algebra, A.A=A2.
2.2 A decimal 92 is the equivalent of an octal 5C.
2.3 Multiplexer is a circuit which receives binary information from one of the multiple input lines
and passes it to the single output line.
2.4 Programmed I/O is more efficient than the interrupt driven I/O.
2.5 In paged memory it is necessary that the pages of a process are loaded contiguously in the
main memory.
2.6 The arithmetic shift treats the data as signed integer and does not shift the sign bit.
2.7 Simplified expression for the boolean expression A'B+ABC'+ABC is B.
2.8 The logic circuit for a half adder consists of an OR and an AND gate.
2.9 The conditional control statement if (P=1) then (R1 <-- R2) else if (Q=1) then (R1 <-- R3) can
be represented by two register transfer statements
P: R1 <-- R2
P'Q: R1 <-- R3
2.10 Cycle Stealing by DMA controller has no effect on CPU operation.

3. Match words and phrases in column X with the closest related meaning/word(s)/phrase(s) in column Y. Enter your selection in the “tear-off” answer sheet attached to the question paper, following instructions therein. (1x10)
                                     X                                                                                    Y
3.1 The basic logic circuit that performs manipulation of binary               A. ROM
information
3.2 A register that goes through a predetermined sequence of                   B. Pipelining
states upon the application of input pulses
3.3 This is used to determine the type of instruction in the                        C. Trap
decode phase of the instruction cycle
3.4 This helps in accessing consecutive elements of a data                       D. VLSI
array
3.5 This is used to hold the most recently referenced page table               E. D7
entries
3.6 A technique of decomposing a sequential process into sub                 F. Index Register
processes each one executing in a special dedicated
segment
3.7 This type of interrupt arise from the illegal or erroneous use            G. TLB (Translation Look                                                                                                                              aside Buffer)
                                                                                                                      of an instruction or data
3.8 The library function may be stored in this type of memory               H. Counter
3.9 Used for multiplication of binary integers                                         I. Booth Algorithm
3.10 This contains thousands of gates within a single package              J. Gate
                                                                                                                  K. Accumulator
                                                                                                                  L. Decoder
                                                                                                                  M. RAM
                                                                                                                  N. Banker’s Algorithm

4. Each statement below has a blank space to fit one of the word(s) or phrase(s) in the list below. Enter your choice in the “tear-off” answer sheet attached to the question paper,following instructions therein. (1x10)

A. CMA                                          B. Control Memory                                    C. RS Flip Flop
D. Minterm                                     E. Odd                                                         F. Zero Address
G. Postfix                                       H. Karnaugh’s map                                     I. D Flip Flop
J. Even                                            K. One Address                                          L. Strobe
M. Condition Code                         N. Prefix

4.1 A JK flip flop is a refinement of ________ flip flop.
4.2 Each combination of variables in a truth table is called a ________.
4.3 The parity method detects the presence of ________ number of errors.
4.4 In microprogrammed control, the control information is stored in a ________.
4.5 The pseudo instruction for complementing the accumulator is ________.
4.6 A stack organized computer has ________ instruction format.
4.7 One way of achieving the asynchronous data transfer is by means of a ________ pulse
supplied by one of the units to indicate to the other unit when the transfer has to occur.
4.8 ________ are used to simplify Boolean expressions.
4.9 AB*CD*+ is ________ form of an arithmetic expression.
4.10 ________ bits are used to check the result of the last arithmetic operation performed in ALU
(arithmetic and logic unit).

PART TWO
(Answer ALL questions)
5.
a) Represent the decimal number 46.5 as a floating point binary number with 24 bits. The
normalized fraction mantissa has 16 bits and the exponent has 8 bits.
b) How many address lines and input, output data lines are needed for a memory unit of 64K X 8
(where 64K is the number of words and word length is 8 bits).
c) Simplify the following Boolean function using three variable K map?
F(x,y,z) = (2, 3, 5, 6, 7)
(6+3+6)
6.
a) An 8-bit register contains the binary value 10011100. What is the register value after an
arithmetic shift right? Starting from the initial number 10011100, determine the register value
after an arithmetic shift left and state whether there is an overflow.
b) What do you mean by asynchronous data transfer? Explain strobe controlled and hand
shaking mechanism for asynchronous data transfer?
c) What is the advantage of having different type of addressing modes? Explain Relative
Addressing mode with the help of an example.
(4+6+5)
7.
a) An instruction at address 021 in the basic computer has I=0, an operation code of the AND
instruction and an address part equal to 083 (all numbers are in hexadecimal). The memory
word at 083 contains the operand B8F2 and the content of AC is A937. Go over the instruction
cycle and determine the contents of the following registers at the end of the execution phase:
PC, AC, DR, AC and IR.
b) Compare and Contrast the interrupt driven I/O and data transfer between memory and I/O
device through the DMA controller.
(6+9)
8.
a) What is virtual memory? Explain its implementation.
b) Write an assembly language program to count the number of ‘*’ in a sequence of 20
characters stored at location X and put the result at location Y.
c) Draw a flow chart depicting the divide operation of fixed point binary numbers.
(5+5+5)

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