A Level January, 2013 A4-R4: COMPUTER SYSTEM ARCHITECTURE

A Level January, 2013

A4-R4: COMPUTER SYSTEM ARCHITECTURE

TOTAL TIME: 3 HOURS TOTAL MARKS: 100
(PART ONE – 40; PART TWO – 60)

PART ONE

(Answer all the questions)

1. Each question below gives a multiple choice of answers. Choose the most appropriate one and enter in the “tear-off” answer sheet attached to the question paper, following instructions therein. (1x10)
1.1 Conversion of hexadecimal number 6B2 to its binary number equivalent is
A) 111100011011
B) 011011010101
C) 011010110010
D) 011011000010
1.2 Which of the following registers is used to keep track of the address of the next instruction?
A) Memory Address Register
B) Instruction Register
C) Program Counter
D) Memory Data Register

A Level July, 2013 A4-R4: COMPUTER SYSTEM ARCHITECTURE

A Level July, 2013

A4-R4: COMPUTER SYSTEM ARCHITECTURE

TOTAL TIME: 3 HOURS TOTAL MARKS: 100
(PART ONE – 40; PART TWO – 60)

PART ONE

(Answer all the questions)

1. Each question below gives a multiple choice of answers. Choose the most appropriate one and enter in the “OMR” answer sheet supplied with the question paper, following instructions therein. (1x10)
1.1 Which one among the following 2 Input logic gates can be used to implement any other 2 Input
Logic gates?
A) AND
B) EX-OR
C) OR
D) NOR
1.2 What is the FAN-OUT of any standard TTL Logic Gate?
A) 2
B) 1
C) 10
D) 5

A Level January, 2014 A4-R4: COMPUTER SYSTEM ARCHITECTURE

A Level January, 2014
A4-R4: COMPUTER SYSTEM ARCHITECTURE

TOTAL TIME: 3 HOURS TOTAL MARKS: 100
(PART ONE – 40; PART TWO – 60)

PART ONE

(Answer all the questions)

1. Each question below gives a multiple choice of answers. Choose the most appropriate one and enter in the “OMR” answer sheet supplied with the question paper, following instructions therein. (1x10)

1.1 The no. of minterms in a truth table of n variables
A) n2
B) 2n
C) 2*n
D) n!
1.2 The algebraic function for XOR logic gate with two inputs A and B is
A) AA’ + BB’
B) A(A+B)
C) AB+A’B’
D) A’B+AB’

Nielit July, 2014 A4-R4: COMPUTER SYSTEM ARCHITECTURE

Nielit July, 2014
A4-R4: COMPUTER SYSTEM ARCHITECTURE
NOTE:
1. There are TWO PARTS in this Module/Paper. PART ONE contains FOUR questions and
PART TWO contains FIVE questions.
2. PART ONE is to be answered in the OMR ANSWER SHEET only, supplied with the
question paper, as per the instructions contained therein. PART ONE is NOT to be
answered in the answer book.
3. Maximum time allotted for PART ONE is ONE HOUR. Answer book for PART TWO will be
supplied at the table when the answer sheet for PART ONE is returned. However,
candidates, who complete PART ONE earlier than one hour, can collect the answer book for
PART TWO immediately after handing over the answer sheet for PART ONE.

TOTAL TIME: 3 HOURS TOTAL MARKS: 100
(PART ONE – 40; PART TWO – 60)

PART ONE

(Answer all the questions)

1. Each question below gives a multiple choice of answers. Choose the most appropriate one and enter in the “OMR” answer sheet supplied with the question paper, following instructions therein. (1x10)

1.1 Von Neumann architecture of computer is mainly characterized by
A) Separate storage and signal path ways for their instructions and data
B) Stored- program concept emphasizing storing of data as well as the instructions to
manipulate that data, in the same way
C) Swiftly execution of program
D) None of the above
1.2 A refinement of SR flip-flop in which indeterminate condition of the SR type is defined as
A) JK Flip-flop
B) D Flip-flop
C) T Flip-flop
D) None of the above